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AS4C64M16MD1 confidential 1 rev 1.0 mar/2014 1 gb (64 m x 16 bit) 1.8v high performance mobile ddr sdram confidential advanced (rev. 1.0, mar . /2014) features - 4 banks x 16m x 16 organization - data mask for write control (dm) - four banks controlled by ba0 & ba1 - programmable cas latency: 2, 3 - programmable wrap sequence: sequential or interleave - programmable burst length: 2, 4, 8 or 16 for sequential type 2, 4, 8 or 16 for interleave type - automatic and controlled precharge command - powe r down mode - auto refresh and self refresh - refresh interval: 8192 cycles/64ms - double data rate (ddr) - bidirectional data strobe (dqs) for input and output data, active on both edges - differential clock inputs clk and /clk - power supply 1.7v - 1.95v - drive stren gth (ds) option: full, 1/2, 1/4, 1/8 - auto temperature - compensated self refresh (auto tcsr) - partial - array self refresh (pasr) option: full, 1/2, 1/4, 1/8, 1/16 - deep power down (dpd) mode - operating temperature range ? extended - 25c to 85c ? industrial - 40c to 85c - 60 ball f p bga package all products rohs compliant description the AS4C64M16MD1 is a four bank mobile ddr dram organized as 4 banks x 16m x 16. it achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. all of the control, address, circuits is synchro nized with the positive edge of an externally sup - plied clock. i/o transactions are possible on both edges of dqs. operating the four memory banks in an inter leaved fashion allows random access operation to occur at a higher rate than is possible with standard drams. a sequential and gapless data rate is pos sible depending on burst length, cas latency and speed grade of the device. additionally, the device supports low power sav ing features like pasr, auto - tcsr, dpd as well as options for different drive strength. its ideally suit - able for mobile application. 6 unit system frequency (f ck ) 166 mhz mhz clock cycle time (t ck3 ) 6 . 0 ns output data access time (t ac (cl3) ) 5 . 0 ns ordering information part no. clock frequency vdd/vddq organisation package as4c64 m16md1 - 6bcn* ddr333 166mhz 1.8v/1.8v 16 m x 16 bits x 4 banks 60 - fp bga AS4C64M16MD1 - 6bin* ddr333 166mhz 1.8v/1.8v 16m x 16 bits x 4 ba nks 60 - fpbga *b = fpbga package * c = usually represents commercial temperature but in this case it extended ( - 25c to +85c) i = industrial temperature - 40c to 85c * n = rohs compliant
AS4C64M16MD1 confidential 2 rev 1.0 mar/2014 block diagram
AS4C64M16MD1 confidential 3 rev 1.0 mar/2014 60ball(6x10) csp 1 2 3 7 8 9 a v ss dq15 v ssq v ddq dq0 v dd b v ddq dq13 dq14 dq1 dq2 v ssq c v ssq dq11 dq12 dq3 dq4 v ddq d v ddq dq9 dq10 dq5 dq6 v ssq e v ssq udqs dq8 dq7 ldqs v ddq f v ss udm n.c. a13 ldm v dd g cke ck ck we cas ras h a9 a11 a12 cs ba0 ba1 j a6 a7 a8 a10/ap a0 a1 k v ss a4 a5 a2 a3 v dd 60 ball bga configuration top view 9 8 7 6 5 4 1 a b c d e f g h j k pin names clk, clk differential clock input cke clock enable cs chip select ras row address strobe cas column address strobe we write enable ldqs, udqs data strobe (bidirectional) a 0 C a 13 address inputs ba0, ba1 bank select dq 0 C dq 15 data input/output ldm, udm data mask v dd power (1.7v - 1.95v) v ss gro und v ddq power for i/os (1.7v - 1.95v) v ssq ground for i/os
AS4C64M16MD1 confidential 4 rev 1.0 mar/2014 signal pin description pin type signal polarity function clk clk input pulse positive edge the system clock input. all inputs except dqs and dms are sampled on the rising edge of c lk. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder whe n low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. input pulse active low when sampled at the positive rising edge of the clock, cas, ras, and we define the c ommand to be executed by the sdram. ras, cas we a0 - a13 input level during a bank activate command cycle, a0 - a13 defines the row address (ra0 - ra13) when sampled at the rising clock edge. during a read or write command cycle, a0 - a9 defines the colu mn address (ca0 - ca9) when sampled at the rising clock edge. in addition to the column address, a10 is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the ba nk to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged simultaneously regard less of state of ba0 and ba1. dqx input/ output level data input/output pins operate in the same manner as conventional drams. ba0, ba1 input level selects which bank is to be active. ldqs, udqs input/ output level data input/output are synchronous edges of the dqs. ldqs for dq0 - dq7, udqs for dq8 - dq15. active on both edges for data input/output. center aligned to input data and edge aligned to output data. udm, ldm input pulse active high in write mode, dqm has a latency of zero and operates as a w ord mask by allowing input data to be written if it is low but blocks the write operation if is high. if its high, ldm cor responds to dq0 - dq7, and udm corresponds to data on dq8 - dq15. vdd, vss supply power and ground for the input buffers and the cor e logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity.
AS4C64M16MD1 confidential 32 rev 1.0 mar/2014 mode register set the mode register stores the data for controlling the various operating modes of the mobile ddr, includes cas latency, addressing mode, burst length, test mode, and various vendor specific options. the default value of the mode register is not defined. therefore the mode register must be written after power up to operate the mobile ddr. the device should be activated with the cke already high prior to writing into the mode register. the mode register is written by using the mrs command. the state of the address signals registered in the same cycle as mrs command is written in the mode register. the value can be changed as long as all banks are in the idle state. the mode register is divided into various fields depending on functionality. the burst length uses a2.. a0, cas latency (read latency from column address) uses a6.. a4. ba0 must be set to low for normal operation. a9.. a13 is reserved for future use. ba1 selects extended mode register setup operation when set to 1. refer to the table for specific codes for various burst length, addressing modes and cas latencies.
AS4C64M16MD1 confidential 3 3 rev 1.0 mar/2014 emrs the extended mode register is responsible for setting the drive strength options and partial array self refresh. the emrs can be programmed by performing a normal mode register setup operation and setting the ba1=1 and ba0=0. in order to save power consumption, the mobile ddr sdram has five (pasr) opt ions: full array, 1/2, 1/4 ,1/8, 1/16 of full array. additionally, the device has internal temperature sensor to control self refresh cycle automatically according to the two temperature range; max. 40 deg c, and max. 85 deg c. this is the device internal temperature compensated self refresh(tcsr). the device has four drive strength options: full, 1/2, 1/4 or 1/8.
AS4C64M16MD1 confidential 34 rev 1.0 mar/2014 signal and timing description general description the 1g bit mobile ddr is a 128m byte mobile ddr sdram. it consists of four banks. each bank is organized as 16384 rows x 1024 columns x 16 bits. read and write accesses are burst oriented. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and the row to be accessed. ba1 and ba0 select the bank, address bits a13.. a0 select the row. address bits a9.. a0 registered coincident with the read or write commands are used to select the starting column loca tion for the burst access. the regular single data rate sdram read and write cycles only use the rising edge of the external clock input. for the mobile sdram the special signals dqsx (data strobe) are used to mark the data valid window. during read bursts, the data valid window coincides with the high or low level of the dqsx signals. during write bursts, the dqsx signal marks the center of the valid data window. data is available at every rising and falling edge of dqsx, therefore the data transfer rate is doubled. for read accesses, the dqsx signals are aligned to the clock signal clk. special signal description clock signal the mobile ddr operates with a differential clock (clk and clk) input. clk is used to latch the address and command signals. data input and dmx signals are latched with dqsx. the minimum and maximum clock cycle time is defined by t ck . the minimum and maximum clock duty cycle are specified using the minimum clock high time t ch and the minimum clock low time t cl respectively. command inputs and addresses like single data rate sdrams, each combination of ras, cas and we input in conjunction with cs input at a rising edge of the clock determines a mobile ddr command.
AS4C64M16MD1 confidential 35 rev 1.0 mar/2014 data strobe and data mask operation at burst reads the data strobes provide a 3 - state output signal to the receiver circuits of the controller during a read burst. the data strobe signal goes 1 clock cycle low before data is driven by the mobile ddr and then toggles low to high and high to low till the end of the burst. cas latency is specified to the first low to high transition. the edges of the output data signals and the edges of the data strobe signals during a read are nominally coincident with edges of the input clock. the tolerance of these edges is specified by the parameters t ac and t dqsck and is referenced to the crossing point of the clk and /clk signal. the t dqsq timing parameter describes the skew between the data strobe edge and the output data edge. the following table summarizes the mapping of ldqs, udqs, ldm and udm signals to the data bus. mapping of ldqs, udqs, ldm and udm data strobe signal data mask signal controlled data bus ldqs ldm dq7 .. dq0 udqs udm dq8 .. dq15 the minimum time during which the output data is valid is critical for the receiving device. this also applies to the data strobe dqs during a read since it is tightly coupled to the output data. the parameters t qh and t dqsq define the mini - mum output data valid window. prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit from hi - z to a valid logic low. this is referred to as the data strobe read preamble t rpre . this transition happens one clock prior to the first edge of valid data. once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe sig nals transit from a valid logic low to hi - z. this is referred to as the data strobe read post amble t rpst .
AS4C64M16MD1 confidential 36 rev 1.0 mar/2014 data output timing - t ac and t dqsck
AS4C64M16MD1 confidential 37 rev 1.0 mar/2014 operation at burst write during a write burst, control of the data strobe is driven by the memory controller. the ldqs, udqs signals are centered with respect to data and data mask. the tolerance of the data and data mask edges versus the data strobe edges during writes are specified by the setup and hold time parameters of data (t qdqss & t qdqsh ) and data mask (t dmdqss & t dmdqsh ). the input data is masked in the same cycle when the corresponding ldm, udm signal is high (i.e. the ldm,udm mask to write latency is zero.) prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal ldqs, udqs changes from hi - z to a valid logic low. this is referred to as the data strobe write preamble. once the burst of write data is concluded, given no subsequent burst write operation is initiated, the data strobe signal ldqs,udqs transits from a valid logic low to hi - z. this is referred the data strobe w rite post amble , t wpst . for mobile drr data is written with a delay which is defined by the parameter t dqss, write latency). this is different than the single data rate sdram where data is written in the same cycle as the write command is issued.
AS4C64M16MD1 confidential 38 rev 1.0 mar/2014 power - up sequence the following sequence is highly recommended for power - up : 1. apply power and start clock. maintain cke and the other pins are in nop conditions at the input 2. apply v dd before or at the same time as v ddq , apply v ddq before or at the same time as v ref , v tt 3. start clock, maintain stable conditions for 200 us 4. apply nop and set cke to high 5. apply all bank precharge command 6. issue auto refresh command twice and must satisfy minimum t rfc 7. issue mrs (mode register set command) 8. issue a emrs (extended mode register set command), not necessary mode register set timing the mobile ddr should be act ivat ed with ck e already high prior to writing into the mode register. two c lock cycles are required complete the w rite operation in the mode register. the mo de register content s can be changed using the sam e com mand and clock cycle requirements during operat ion as long as all banks are in t he idle state.
AS4C64M16MD1 confidential 39 rev 1.0 mar/2014 bank activation command (act) the bank activation command is initiated by issuing an act command at the rising edge of the clock. the mobile ddr has 4 independent banks which are selected by the two bank select addresses (ba0, ba1). the bank activation command must be applied before any read or write operation can be executed. the delay from the bank activation command to the first read or write command must meet or exceed the minimum of ras to cas delay time (t rcdrd min . for read commands and t rcdwr min. for write commands). once a bank has been activated, it must be precharged before another bank activate command can be applied to the same bank. the minimum time interval between interleaved bank activate commands (bank a to bank b and vice versa) is the bank to bank activation delay time (t rrd min).
AS4C64M16MD1 confidential 40 rev 1.0 mar/2014 precharge command this command is used to precharge or close a bank that has been activated. precharge is initiated by issuing a precharge command at the rising edge of the clock. the precharge command can be used to precharge each bank respectively or all banks simultaneously. the bank addresses ba0 and ba1 select the bank to be precharged. after a precharge command, the analog delay t rp has to be met until a new activate command can be initiated to the same bank. table precharge control
AS4C64M16MD1 confidential 41 rev 1.0 mar/2014 self refresh the self refresh mode can be used to retain the data in the mobile ddr if the chip is powered down. to set the mobile ddr into a self refreshing m ode, a self refresh command must be issued and cke held low at the rising edge of the clock. once the self refres h command is initiated, cke must stay low to keep the device in self refresh mode. during the self refresh mode, all of the external control signals are disabled except cke. the clock is internally disabled during self refresh operation to reduce power. an internal timing generator guarantees the self - refreshing of the memory content.
AS4C64M16MD1 confidential 42 rev 1.0 mar/2014 auto refresh the auto refresh function is initiated by issuing an auto refresh command at the rising edge of the clock. all banks must be precharged and idle before the auto refresh command is applied. no control of the external address pins is required once this cycle has started. all necessary addresses are generated in the device itself. when the refresh cycle has completed, all banks will be in the idle state. a delay between the auto refresh command and the next activate command or subsequent auto refresh command must be greater than or equal to the t rfc (min). power down mode the power down mode is entered when cke is set low and exited when cke is set high. the cke signal is sampled at the rising edge of the clock. once the power down mode is initiated, all of the receiver circuits except clk and the cke circuits are gated off to reduce power consumption. all banks can be set to idle state or stay activate during power down mode, but burst activity may not be performed. after exiting from power down mode, at least one clock cycle of command delay must be inserted before starting a new command. during power down mode, refresh operations cannot be performed; therefore, the device cannot remain in power down mode longer than the refresh period ( t ref ) of the device.
AS4C64M16MD1 confidential 43 rev 1.0 mar/2014 deep power down mode the deep power down mode is a unique function with very low standby currents. all internal vol ta ge generators inside the mobile ddr are stopped and all memory data is lost in this mode. to enter the deep power down mode all banks must be precharged. the deep power down mode has to be maintained for a minimum of 100s.
AS4C64M16MD1 confidential 44 rev 1.0 mar/2014 deep power down exit the deep power down mode is exited by asserting cke high. after the exit, the following sequence is needed to enter a new command : 1. maintain nop input conditions for a minimum of 200 us 2. issue precharge commands for all banks of the device 3. issue two or more auto refresh commands and satisfy minimum t rfc 4. issue a mode register set command to initialize the mode register 5. issue an extended mode register set command to initialize the extende d mode register
AS4C64M16MD1 confidential 45 rev 1.0 mar/2014 burst mode operation burst mode opera tion is used to provide a constant flow of data to the memory (write cycle) or from the memory (read cycle). the burst length is programmable and set by address bits a0 - a3 during the mode register setup command. the burst length controls the number of wo rds that will be output after a read command or the number of words to be input after a write command. one word is 32 bits wide. the sequential burst length can be set to 2, 4, 8 or 16 data words.
AS4C64M16MD1 confidential 46 rev 1.0 mar/2014 burst read operation: (read) the burst read operation is initiated by issuing a read command at the rising edge of the clock after t rcd from the bank activation. the address inputs (a8.. a0) determine the starting address for the burst. the burst length (2, 4 or 8) must be defined in the mode register. the first data after the read command is available depending on the cas latency. the subsequent data is clocked out on the rising and falling edge of ldqs, udqs until the burst is completed. the ldqs, udqs signa ls are generated by the mobile ddr during the burst read operation.
AS4C64M16MD1 confidential 47 rev 1.0 mar/2014 burst write operation (write) the burst write is initia ted by issuing a write command at the rising edge of the clock. the address inputs (a8 .. a0) determine starting column address. data for the first burst write cycle must be applied on the dq pins on the first rise edge of ldqs, udqs follow write command. the time between the write command and the first corresponding edge of the data strobe is t dqss . the remaining data inputs must be supplied on each subsequent rising and falling edge of the data strobe until the burst length is completed. when the burst ha s been finished, any additional data supplied to the dq pins will be ignored.
AS4C64M16MD1 confidential 48 rev 1.0 mar/2014 burst stop command (bst) a burst stop is initiated by issuing a burst stop command at the rising edge of the clock. the burst stop command has the fewest restrictions, making it the easiest method to terminate a burst operation before i t has been completed. when the burst stop command is issued during a burst read cycle, read data and ldqs, udqs go to a high - z state after a delay which is equal to the cas latency set in the mode register. the burst stop latency is equal to the cas latenc y cl. the burst stop command is not supported during a write burst operation. burst stop is also illegal during read with auto - precharge
AS4C64M16MD1 confidential 49 rev 1.0 mar/2014 data mask (ldm, udm) function the mobile ddr has a data mask function that can be used only during write cycles. when the data mask is activated, active high during burst write, the write operation is masked immediately. the ldm, udm to data - mask latency zero. ldm and udm can be issued at the rising or negative edge of data strobe.
AS4C64M16MD1 confidential 50 rev 1.0 mar/2014
AS4C64M16MD1 confidential 51 rev 1.0 mar/2014 write with autoprecharge (write a ) if a8 is high when a write command is issued, the write with auto - precharge function is performed. the internal precharge begins after the write recovery time t wr and t ras (min) are satisfied. if a write with auto precharge command is initiated, the mobile ddr automatically enters the precharge operation at the first rising edge of clk after the last valid edge of dqs (completion of the burst) plus the write recovery time t wr . once the precharge operation has started, the bank cannot be reactivated and the new command can n ot be asserted until the precharge time (t rp ) has been satisfied. if t ras (min) has not been satisfied yet, an internal interlock will delay the precharge operation until it is satisfied.
AS4C64M16MD1 confidential 52 rev 1.0 mar/2014 write interrupted by a precharge a burst write operation can be interrupted before completion of th e burst by a precharge of the same bank. random column access is allowed. a write recovery time (t wr ) is required from the last data to precharge command. when precharge command is asserted, a n y r esidual da t a f rom t he bu r st wri t e c y cle m ust be m a sked by l d m . , udm.
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AS4C64M16MD1 confidential 57 rev 1.0 mar/2014 note: all entries assume the cke was high during the preceding clock cycle note: 1. illegal to bank specifie d states; function may be legal in the bank indicated by bax, depending on the state of that bank note: 2. must satisfy bus contention, bus turn around, write recovery requirements. note: 3. if both banks are idle, and cke is inactive, the device will en ter power down mode. all input buffers except cke, clk and clk# will be disabled. note: 4. if both banks are idle, and cke is deactivated coincidentally with an auto refresh command, the device will enter self refresh mode. all input buffers except cke will be disabled. note: 5. illegal, if t rrd is not satisfied. note: 6. illegal, if t ras is not satisfied. note: 7. must satisfy burst interrupt condition. note: 8. must mask two preceding data bits with the dm pin. note: 9. illegal, if t rcd is not satisfi ed. note: 10. illegal, if t wr is not satisfied. note: 11. illegal, if t rc is not satisfied. abbreviations: h high level l low level x d on t care v valid data input ra row address b a bank address p a precharge all nop no operation ca column addr ess a x address line x
AS4C64M16MD1 confidential 58 rev 1.0 mar/2014 abbreviations: h high level l low level x d on t care v valid data input ra row address b a bank address p a precharge all nop no operation ca column address
AS4C64M16MD1 confidential 59 rev 1.0 mar/2014
AS4C64M16MD1 confidential 60 rev 1.0 mar/2014 idd max specifications and conditions conditions version symbol - 6 unit operating current - one bank active - precharge; trc = trc (min); tck = tck (min); cke = high; cs = high between valid command; address inputs are switching every 2 clock cycles; data bus inputs are stable idd0 55 ma precharge power - down standby current; all banks idle; cke = low; cs = high; tck = tck (min); address and control inputs are switching; data bus inputs are stable idd2p 2 ma precharge power - down standby current; clock stopped; all banks idle; cke = low; cs = high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable idd2ps 2 ma precharge nonpower - down standby current; all banks idle; cke = high; cs = high; tck = tck (min); address and control inputs are switching; data bus inputs are stable idd2n 25 ma precharge nonpowe r - down standby current; clock stopped; all banks idle; cke = high; cs = high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable idd2ns 18 ma active power - down standby current; one bank active; cke = low; cs = high; tck = tck (min); address and control inputs are switching; data bus inputs are stable idd3p 2 ma active power - down standby current; clock stopped; one bank active; cke =low; cs = high; ck = low; ck = high; address and control in puts are switching; data bus inputs are stable idd3ps 2 ma active nonpower - down standby current; one bank active; cke = high; cs = high; tck = tck (min); address and control inputs are switching; data bus inputs are stable idd3n 25 ma active nonpower - down standby current; clock stopped; one bank active; cke = high; cs = high; ck = low; ck = high; address and control inputs are switching; data bus inputs are stable idd3ns 18 ma operating current - burst read; one b ank active; burst length = 4; tck = tck (min); continuous read burst; address inputs are switching every 2 clock cycles; 50% of data changing at every burst; lout = 0 m a idd4r 85 ma operating current - burst write; one bank active; burst length = 4; tck = tck (min); continuous write burst; address inputs are switching every 2 clock cycles; 50% of data changing at every burst idd4w 85 ma auto refresh current; burst refresh; cke = high; address and control inputs are switchi ng; data bus inputs are stable idd5 90 ma deep power down current; address and control inputs are stable; data bus inputs are stable idd8 5 ua
AS4C64M16MD1 confidential 61 rev 1.0 mar/2014 partial array self refresh current (pasr) parameter & test condition extended mod e register a[2:0] tcase [ o c] symb. max. unit note self refresh current self refresh mode cke = 0.2v, tck = infinity, full array activations, all banks 85 o c max. icc6 2.0 ma self refresh current self refresh mode cke = 0.2v, tck = infinit y, 1/2 array activations 85 o c max. icc6 1.6 ma self refresh current self refresh mode cke = 0.2v, tck = infinity, 1/4 array activation 85 o c max. icc6 1.4 ma self refresh current self refresh mode cke = 0.2v, tck = infinity, 1/8 array ac tivation 85 o c max. icc6 1.2 ma self refresh current self refresh mode cke = 0.2v, tck = infinity, 1/16 array activation 85 o c max. icc6 1.2 ma
AS4C64M16MD1 confidential 62 rev 1.0 mar/2014 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out - 0.5 ~ 2.7 v voltage on v dd supply relative to v ss v dd , v ddq - 0.5 ~ 2.7 v storage temperature t stg - 55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma note: permanent device damage may occur if absolute maximum rating s are exceeded. functional operation should be restricted to recommended operating co ndition exposure to higher than recommended voltage for extended periods of time could affect device reliability. capacitance ( v dd = 1.8v, t a = 25c, f = 1mhz ) pa rameter symbol min max unit input capacitance ( a 0 ~a 13 , ba 0 ~ba 1, cke, cs, ras, cas, we ) c in1 1.5 3.0 pf input capacitance ( ck, ck ) c in2 1.5 3.0 pf data & dqs input/output capacitance ( dq 0 ~dq 15 ) c out 3.0 5.0 pf input capacitance ( dms ) c in3 3.0 5.0 pf
AS4C64M16MD1 confidential 63 rev 1.0 mar/2014 power & dc operating conditions (lvcmos in/out) recommended operating conditions ( voltage referenced to v ss = 0v ) parameter symbol min typ max unit device supply voltage v dd 1.7 1.8 1.95 v output supply voltage v ddq 1.7 1.8 1.95 v input logic high voltage v ih 0.7*v ddq - v ddq +0.30 v input logic low voltage v il - 0.3 - 0.3*v ddq v input leakage current i i - 2 - 2 ua output leakage current ioz - 5 - 5 ua ac input operating conditions recommended operating conditions ( voltage referenced to v ss = 0v, v dd = 1.7v ~ 1.95v) parameter symbol min typ max unit input high (logic 1) voltage; dq v ih v ccq *0.8 - v ccq +0.3 v input low (logic 0) voltage; dq v il - 0.3 - 0.2* v ddq v clock input crossing point voltage; ck and ck v ix 0.4*v ddq - 0.6*v ddq v ac operating test conditions recommended operating conditions ( voltage referenced to v ss = 0v, v dd = 1.7v ~ 1.95v) parameter value unit ac input levels (vih/vil) 0.8*vddq / 0.2*vddq v input timing measurement reference level 0.5*vddq v input signal mini mum slew rate 1.0 v/ns output timing measurement reference level 0.5*vddq v output load condition see below figures
AS4C64M16MD1 confidential 64 rev 1.0 mar/2014 ac characteristic s - 6 parameter symbol min max units notes output data access time from ck/ck t ac 2 5 ns 3 ck high - level width t ch 0.45 0.55 t ck ck low - level width t cl 0.45 0.55 t ck clock cy cle time cl = 3 t ck (3) 6 - ns 1 dq and dm input hold time relative to dqs t dh 0.6 ns 5,6 dq and dm input setup time relative to dqs t ds 0.6 ns 5,6 dq and dm input pulse width (for each input) t dipw 1.6 ns ac cess window of dqs from ck/ck t dqsck 2 5 ns dqs input high pulse width t dqsh 0.4 0.6 t ck dqs input low pulse width t dqsl 0.4 0.6 t ck dqs - dq skew, dqs to last dq valid, per group, per access t dqsq 0.5 ns 1 write command to first dqs latching transition t dqss 0.75 1.25 t ck half clock period t hp t t cl ns data - out high - impedance window from ck/ck t hz 0.4 0.6 t ck data - out low - imp edance window from ck/ck t lz 1 ns address and control input hold time t ih 1.1 ns 1 address and control input setup time t is 1.1 ns 1 load mode register command cycle time t mrd 2 t ck dq - dqs hold, dqs to first dq to go non - valid, per access t qh t - t qhs ns data hold skew factor t qhs 0.65 ns active to precharge command t ras 42 70k ns active to read with auto precharge command t rap 15 ns active to a ctive/auto refresh command period t rc 60 ns auto refresh command period t rfc 72 ns active to read or write delay t rcd 18 ns precharge command period t rp 18 ns ac timing parameters & specification
AS4C64M16MD1 confidential 65 rev 1.0 mar/2014 ac characteristics - 6 parameter symb ol min max units notes dqs read preamble t rpre 0.9 1.1 t ck dqs read post amble t rpst 0.4 0.6 t ck active bank a to active bank b command t rrd 12 ns dqs write preamble t wpre 0.25 t ck dqs write preamble setup time t wpres 0 ns 4 dqs write post amble t wpst 0.4 0.6 t ck write recovery time t wr 15 ns internal write to read command delay t wtr 2 t ck average periodic refresh interval t refi 7.8 us power down exit time t pdex 1*t + t is ns
AS4C64M16MD1 confidential 66 rev 1.0 mar/2014 1. input setup/hold slew rate de rating input setup/hold slew rate tis tih (v/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 this derating table is used to increase t is /t ih in the case where the input slew rate is below 1.0v/ns. 2. minimum 3clk of t d a l ( = twr + trp) is required becaus e it need minimum 2clk for twr and minimum 1clk for trp. 3. tac(mi n) value is measured at the high vdd(1.95v) and cold temperature( - 25 c). tac (max) value is measured at the low vdd(1.7v) and hot temperature(85 c). tac is measured in the device with half d river strength and under the ac output load condition. 4. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going from high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 5. i/o setup/hold slew rate derating i/o setup/hold slew rate tds tdh (v/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 1.0v/ns. 6. i/o delta rise/fall rate(1/slew - rate) derating delta rise/fall rate tds tdh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 this derating table is used to increase tds/tdh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calculated as 1/slewrate1 - 1/slewrate2. for example, if slew rate 1 = 1.0v/ns and slew rate 2 =0.8v/ns, then the delta rise/fall rate = - 0.25ns/
AS4C64M16MD1 confidential 67 rev 1.0 mar/2014
AS4C64M16MD1 confidential 68 rev 1.0 mar/2014 revision history rev. history date remark 1.0 release mar . 201 4 sm alliance memory inc. reserves the rights to change the specifications and products without notice. alliance memory, inc., 551 taylor way, suite #1, san carlos, ca 94070, usa tel: +1 650 610 6800 fax: +1 650 620 9211

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